DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 288

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7 Background Debug Module (S12XBDMV2)
7.3.2.2
Register Global Address 0x7FFF06
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte
of the condition code register of the user’s program. It is also used for temporary storage in the standard
BDM firmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.
7.3.2.3
Register Global Address 0x7FFF07
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR HIGH holding register is used to save the high
byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be
written to modify the CCR value.
288
Special Single-Chip Mode
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
R
All Other Modes
BDM CCR LOW Holding Register (BDMCCRL)
BDM CCR HIGH Holding Register (BDMCCRH)
0
0
7
When BDM is made active, the CPU stores the content of its CCR
in the BDMCCRL register. However, out of special single-chip reset, the
BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the
CCR
BDMCCRL register is read zero.
Reset
L
W
= Unimplemented or Reserved
R
register in this CPU mode. Out of reset in all other modes the
Figure 7-5. BDM CCR HIGH Holding Register (BDMCCRH)
Figure 7-4. BDM CCR LOW Holding Register (BDMCCRL)
CCR7
6
0
0
7
1
0
MC9S12XE-Family Reference Manual , Rev. 1.23
CCR6
1
0
6
0
0
5
CCR5
0
0
5
NOTE
0
0
4
CCR4
0
0
4
0
0
3
CCR3
3
1
0
CCR10
0
2
CCR2
0
0
2
L
register
Freescale Semiconductor
CCR9
0
1
CCR1
0
0
1
CCR8
CCR0
0
0
0
0
0