DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 379

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 10-25
Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is
running on the RISC core. They both have a critical section of code that accesses the same system resource.
To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence
must be embedded in a semaphore lock/release sequence as shown.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
set_xgsem: 1 is written to XGSEM[n] (and 1 is written to XGSEMM[n])
clr_xgsem: 0 is written to XGSEM[n] (and 1 is written to XGSEMM[n])
ssem:
csem:
gives an example of the typical usage of the XGATE hardware semaphores.
LOCKED BY
clr_xgsem
Executing SSEM instruction (on semaphore n)
Executing CSEM instruction (on semaphore n)
S12X_CPU
ssem &
set_xgsem
Figure 10-24. Semaphore State Transitions
MC9S12XE-Family Reference Manual Rev. 1.23
clr_xgsem
ssem & set_xgsem
UNLOCKED
csem
ssem
LOCKED BY
XGATE
csem
Chapter 10 XGATE (S12XGATEV3)
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