DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 188

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2 Port Integration Module (S12XEPIMV1)
Port J pin PJ[3] can be used for general purpose I/O.
Port J pin PJ[2] can be used for either general purpose I/O or as chip select output.
Port J pin PJ[1] can be used for either general purpose I/O, or with the SCI2 subsystem.
Port J pin PJ[0] can be used for either general purpose I/O, or with the SCI2 subsystem or as chip select
output.
2.4.3.12
This port is associated with the ATD0.
Port AD0 pins PAD[15:0] can be used for either general purpose I/O, or with the ATD0 subsystem.
2.4.3.13
This port is associated with the ATD1.
Port AD1 pins PAD[31:16] can be used for either general purpose I/O, or with the ATD1 subsystem.
2.4.3.14
This port is associated with the TIM module.
Port R pins PR[7:0] can be used for either general-purpose I/O, or with the channels of the standard Timer.
The TIM channels can be re-routed.
2.4.3.15
This port is associated with SCI7-4.
Port L pins PL[7:6] can be used for either general purpose I/O, or with SCI7 subsystem.
Port L pins PL[5:4] can be used for either general purpose I/O, or with SCI6 subsystem.
Port L pins PL[3:2] can be used for either general purpose I/O, or with SCI5 subsystem.
Port L pins PL[1:0] can be used for either general purpose I/O, or with SCI4 subsystem.
2.4.3.16
This port is associated with SCI3, IIC0 and chip selects.
Port L pins PL[7:6] can be used for either general purpose I/O, or with SCI3 subsystem.
Port L pins PL[5:4] can be used for either general purpose I/O, or with IIC0 subsystem.
Port L pins PL[3:0] can be used for either general purpose I/O, or with chip selects.
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Port AD0
Port AD1
Port R
Port L
Port F
MC9S12XE-Family Reference Manual , Rev. 1.23
Freescale Semiconductor