DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 488

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.4
11.4.1
11.4.1.1
The IPLL is used to run the MCU from a different time base than the incoming OSCCLK.
shows a block diagram of the IPLL.
For increased flexibility, OSCCLK can be divided in a range of 1 to 64 to generate the reference frequency
REFCLK using the REFDIV[5:0] bits. This offers a finer multiplication granularity. Based on the
SYNDIV[5:0] bits the IPLL generates the VCOCLK by multiplying the reference clock by a multiple of
2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,4,6,8,...
to 62 to generate the PLLCLK.
Several examples of IPLL divider settings are shown in
settings are not recommended. The following rules help to achieve optimum stability and shortest lock
time:
488
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
.
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
•
•
EXTAL
XTAL
Use lowest possible f
Use highest possible REFCLK frequency f
Supplied by:
Functional Description
Functional Blocks
Phase Locked Loop with Internal Filter (IPLL)
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
V
V
CONSUMPTION
DDPLL
DD
OSCILLATOR
REDUCED
/V
If (PLLSEL = 1) then f
IF POSTDIV = $00 the f
SS
/V
SSPLL
OSCCLK
VCO
MONITOR
f PLL
CLOCK
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 11-15. IPLL Functional Diagram
/ f
=
REF
2 f OSC
PROGRAMMABLE
×
REFERENCE
ratio (SYNDIV value).
REFDIV[5:0]
DIVIDER
BUS
PLL
PROGRAMMABLE
= f
SYNDIV[5:0]
×
DIVIDER
is identical to f
LOOP
----------------------------------------------------------------------------- -
[
PLL
REFDIV
NOTE
REF
/ 2.
REFCLK
.
Table
SYNDIV
FBCLK
+
1
] 2 POSTDIV
[
11-14. Shaded rows indicated that these
VCO
×
DETECTOR
DETECTOR
+
PHASE
1
LOCK
PDET
(divide by one)
PROGRAMMABLE
POSTDIV[4:0]
DIVIDER
POST
]
DOWN
UP
VCOCLK
LOCK
CPUMP
FILTER
AND
Freescale Semiconductor
V
DDPLL
Figure 11-15
/V
PLLCLK
SSPLL
VCO