DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 551

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read: Anytime
Write anytime for output compare function. Writes to these registers have no meaning or effect during
input capture.
All bits reset to zero.
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
14.3.2.15 16-Bit Pulse Accumulator A Control Register (PACTL)
Read: Anytime
Write: Anytime
All bits reset to zero.
Freescale Semiconductor
Module Base + 0x001F
Module Base + 0x0020
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
PAMOD
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
PAEN
Field
6
5
W
W
R
R
Bit 7
Pulse Accumulator A System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable
1 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1).
0 Event counter mode
1 Gated time accumulation mode
0
0
0
7
7
bits in ICPAR are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled.
to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR have no effect.
Pulse Accumulator Input Edge Flag (PAIF) function is enabled. The PACA shares the input pin with IC7.
Figure 14-35. Timer Input Capture/Output Compare Register 7 Low (TC7)
Figure 14-36. 16-Bit Pulse Accumulator Control Register (PACTL)
= Unimplemented or Reserved
PAEN
Bit 6
0
0
6
6
MC9S12XE-Family Reference Manual Rev. 1.23
Table 14-19. PACTL Field Descriptions
PAMOD
Bit 5
5
0
5
0
PEDGE
Bit 4
0
0
4
4
Description
CLK1
Bit 3
0
0
3
3
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
CLK0
Bit 2
2
0
2
0
PAOVI
Bit 1
0
0
1
1
Bit 0
PAI
0
0
0
0
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