DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 271

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3.2.1
Read: Anytime
Write: Anytime
6.3.2.2
Read: Anytime
Write: Anytime
Freescale Semiconductor
Address: 0x0121
Address: 0x0126
IVB_ADDR[7:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
XILVL[2:0]
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
2–0
Field
7–0
W
W
R
R
XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the XGATE
interrupts coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).
Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read
Interrupt Vector Base Register (IVBR)
XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
1
0
0
7
7
Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of
reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to
previous S12 microcontrollers.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of
Figure 6-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
accesses to this register will return all 0.
the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset
vectors (0xFFFA–0xFFFE).
IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”.
= Unimplemented or Reserved
1
0
0
6
6
Figure 6-3. Interrupt Vector Base Register (IVBR)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 6-5. INT_XGPRIO Field Descriptions
Table 6-4. IVBR Field Descriptions
5
1
5
0
0
1
0
0
4
IVB_ADDR[7:0]
4
Description
Description
1
0
0
3
3
2
1
2
0
Chapter 6 Interrupt (S12XINTV2)
XILVL[2:0]
1
0
1
1
1
1
0
0
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