DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 481

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Read: Anytime
Write: Refer to each bit for individual write conditions
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
FM1, FM0
FSTWKP
PLLON
SCME
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
CME
PRE
PCE
5, 4
7
6
3
2
1
0
Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1.
0 Clock monitor is disabled.
1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or Self Clock
Note: Operating with CME=0 will not detect any loss of clock. In case of poor clock quality this could cause
Phase Lock Loop On Bit — PLLON turns on the IPLL circuitry. In Self Clock Mode, the IPLL is turned on, but
the PLLON bit reads the last written value. Write anytime except when PLLSEL = 1.
0 IPLL is turned off.
1 IPLL is turned on.
IPLL Frequency Modulation Enable Bit — FM1 and FM0 enable additional frequency modulation on the
VCOCLK. This is to reduce noise emission. The modulation frequency is f
when PLLSEL = 1. See
Fast Wake-up from Full Stop Bit — FSTWKP enables fast wake-up from full stop mode. Write anytime. If Self-
Clock Mode is disabled (SCME = 0) this bit has no effect.
0 Fast wake-up from full stop mode is disabled.
1 Fast wake-up from full stop mode is enabled. When waking up from full stop mode the system will immediately
RTI Enable During Pseudo Stop Bit — PRE enables the RTI during Pseudo Stop Mode.
Write anytime.
0 RTI stops running during Pseudo Stop Mode.
1 RTI continues running during Pseudo Stop Mode.
Note: If the PRE bit is cleared the RTI dividers will go static while Pseudo Stop Mode is active. The RTI dividers
COP Enable During Pseudo Stop Bit — PCE enables the COP during Pseudo Stop Mode.
Write anytime.
0 COP stops running during Pseudo Stop Mode
1 COP continues running during Pseudo Stop Mode
Note: If the PCE bit is cleared the COP dividers will go static while Pseudo Stop Mode is active. The COP
Self Clock Mode Enable Bit
Normal modes: Write once
Special modes: Write anytime
SCME can not be cleared while operating in Self Clock Mode (SCM = 1).
0 Detection of crystal clock failure causes clock monitor reset (see
1 Detection of crystal clock failure forces the MCU in Self Clock Mode (see
Mode.
resume operation in Self-Clock Mode (see
be set. The system will remain in Self-Clock Mode with oscillator and clock monitor disabled until FSTWKP bit
is cleared. The clearing of FSTWKP will start the oscillator, the clock monitor and the clock quality check. If
the clock quality check is successful, the S12XECRG will switch all system clocks to OSCCLK. The SCMIF
flag will be set. See application examples in
unpredictable operation of the MCU!
In Stop Mode (PSTP=0) the clock monitor is disabled independently of the CME bit setting and any loss
of external clock will not be detected.
Also after wake-up from stop mode (PSTP = 0) with fast wake-up enabled (FSTWKP = 1) the clock monitor
is disabled independently of the CME bit setting and any loss of external clock will not be detected.
will not initialize like in Wait Mode with RTIWAI bit set.
dividers will not initialize like in Wait Mode with COPWAI bit set.
MC9S12XE-Family Reference Manual Rev. 1.23
Table 11-8
Table 11-7. PLLCTL Field Descriptions
for coding.
Section 11.4.1.4, “Clock Quality
Figure 11-19
Description
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
and
Figure
Section 11.5.1.1, “Clock Monitor
11-20.
ref
Section 11.4.2.2, “Self Clock
divided by 16. Write anytime except
Checker”). The SCMIF flag will not
Reset”).
Mode”).
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