DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 375

BOARD DEMO FOR MC9S12XEP100

DEMO9S12XEP100

Manufacturer Part Number
DEMO9S12XEP100
Description
BOARD DEMO FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of DEMO9S12XEP100

Contents
Board, Cables, CD
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DEMO9S12XEP100
Manufacturer:
PANASONIC
Quantity:
46 000
Part Number:
DEMO9S12XEP100
Manufacturer:
Freescale Semiconductor
Quantity:
135
10.3.1.18 XGATE Register 6 (XGR6)
The XGR6 register
Module Base +0x0002C
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
10.3.1.19 XGATE Register 7 (XGR7)
The XGR7 register
Module Base +0x0002E
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
10.4
The core of the XGATE module is a RISC processor which is able to access the MCU’s internal memories
and peripherals (see
by an XGATE request. Then it executes a code sequence (thread) that is associated with the requested
XGATE channel. Each thread can run on a priority level ranging from 1 to 7. Refer to the S12X_INT
Freescale Semiconductor
Reset
Reset
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
XGR6[15:0]
XGR7[15:0]
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
W
R
R
Field
15–0
Field
15–0
15
15
0
0
Functional Description
XGATE Register 6 — The RISC core’s register 6
XGATE Register 7 — The RISC core’s register 7
14
14
0
0
(Figure
(Figure
13
13
Figure
0
0
12
12
0
0
10-20) provides access to the RISC core’s register 6.
10-21) provides access to the RISC core’s register 7.
10-1). The RISC processor always remains in an idle state until it is triggered
MC9S12XE-Family Reference Manual Rev. 1.23
11
11
Figure 10-20. XGATE Register 6 (XGR6)
Figure 10-21. XGATE Register 7 (XGR7)
0
0
Table 10-20. XGR6 Field Descriptions
Table 10-21. XGR7 Field Descriptions
10
10
0
0
0
0
9
9
0
0
8
8
XGR6
XGR7
Description
Description
0
0
7
7
6
0
6
0
0
0
5
5
0
0
4
4
Chapter 10 XGATE (S12XGATEV3)
0
0
3
3
0
0
2
2
1
0
1
0
0
0
0
0
375

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