DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 221

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.4.3
CPU and XGATE accesses are watched in the memory protection unit (See MPU Block Guide). In case of
access violation, the suspect master is acknowledged with an indication of an error; the victim target will
not be accessed.
Other violations MPU is not handling are listed below.
3.4.3.1
A possible access error is flagged by the MMC and signalled to XGATE under the following conditions:
For further details refer to the XGATE Block Guide.
3.4.4
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and
XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus
swapping operations. All internal and external resources are connected to specific target buses (see
Figure 3-23
1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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•
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XGATE performs misaligned word (in case of load-store or opcode or vector fetch accesses).
XGATE accesses the register space (in case of opcode or vector fetch).
XGATE performs a write to Flash in any modes (in case of load-store access).
XGATE performs an access to a secured Flash in expanded modes (in case of load-store or opcode
or vector fetch accesses).
1
Chip Access Restrictions
Chip Bus Control
).
Illegal XGATE Accesses
MC9S12XE-Family Reference Manual Rev. 1.23
Chapter 3 Memory Mapping Control (S12XMMCV4)
221