DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 538

BOARD DEMO FOR MC9S12XEP100

DEMO9S12XEP100

Manufacturer Part Number
DEMO9S12XEP100
Description
BOARD DEMO FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of DEMO9S12XEP100

Contents
Board, Cables, CD
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DEMO9S12XEP100
Manufacturer:
PANASONIC
Quantity:
46 000
Part Number:
DEMO9S12XEP100
Manufacturer:
Freescale Semiconductor
Quantity:
135
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.3.2.2
Read or write: Anytime but reads will always return 0x0000 (1 state is transient).
All bits reset to zero.
14.3.2.3
Read or write: Anytime
All bits reset to zero.
538
Module Base + 0x0001
Module Base + 0x0002
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
FOC[7:0]
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
7:0
W
W
R
R
OC7M7
FOC7
Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note: A channel 7 event, which can be a counter overflow when TTOV[7] is set or A successful channel 7 output
Timer Compare Force Register (CFORC)
Output Compare 7 Mask Register (OC7M)
0
0
0
7
7
compare overrides any channel 6:0 compares. If a forced output compare on any channel occurs at the
same time as the successful output compare, then the forced output compare action will take precedence
and the interrupt flag will not get set.
OC7M6
FOC6
Figure 14-5. Output Compare 7 Mask Register (OC7M)
0
0
0
6
6
Figure 14-4. Timer Compare Force Register (CFORC)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 14-3. CFORC Field Descriptions
OC7M5
FOC5
5
0
0
5
0
OC7M4
FOC4
0
0
0
4
4
Description
OC7M3
FOC3
0
0
0
3
3
OC7M2
FOC2
2
0
0
2
0
OC7M1
Freescale Semiconductor
FOC1
0
0
0
1
1
OC7M0
FOC0
0
0
0
0
0

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