DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 621

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds
2. To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs,
16.3.2.6
This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register.
1. Read: Anytime
Freescale Semiconductor
Module Base + 0x0005
a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state
skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.
reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition.
Write: Anytime when not in initialization mode
OVRIF
RXF
Field
1
0
Reset:
(2)
W
R
Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt
is pending while this flag is set.
0
1
Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO.
This flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier,
matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message
from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag
prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt
is pending while this flag is set.
0
1
MSCAN Receiver Interrupt Enable Register (CANRIER)
WUPIE
The CANRIER register is held in the reset state when the initialization mode
is active (INITRQ=1 and INITAK=1). This register is writable when not in
initialization mode (INITRQ=0 and INITAK=0).
The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization
mode.
0
7
No data overrun condition
A data overrun detected
No new message available within the RxFG
The receiver FIFO is not empty. A new message is available in the RxFG
Figure 16-9. MSCAN Receiver Interrupt Enable Register (CANRIER)
Table 16-11. CANRFLG Register Field Descriptions (continued)
CSCIE
6
0
MC9S12XE-Family Reference Manual Rev. 1.23
RSTATE1
0
5
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
RSTATE0
NOTE
4
0
Description
TSTATE1
0
3
TSTATE0
2
0
Access: User read/write
OVRIE
0
1
RXFIE
0
0
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