DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 197

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3.2
3.3.2.1
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data is read from this register.
Write: Anytime. In emulation modes write operations will also be directed to the external bus.
The MMCCTL0 register is used to control external bus functions, like:
Freescale Semiconductor
Address: 0x000A PRR
1. ROMON is bit[0] of the register MMCTL1 (see
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
•
•
1. Disabled: feature always inactive.
2. Enabled: activity is controlled by the appropriate register bit value.
W
R
Availability of chip selects. (See
Control of different external stretch mechanism. For more detail refer to the S12X_EBI
BlockGuide.
CS0E[1:0], CS1E[1:0],
CS2E[1:0], CS3E[1:0]
CS3E1
Register Descriptions
MMC Control Register (MMCCTL0)
Register Bit
0
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
= Unimplemented or Reserved
CS3E0
0
6
Figure 3-3. MMC Control Register (MMCCTL0)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 3-5. Chip Selects Function Activity
Disabled
CS2E1
NS
5
0
Table 3-5
Figure
(1)
Disabled
3-10)
CAUTION
CS2E0
SS
0
4
and
Table
Enabled
CS1E1
NX
3-6)
Chip Modes
0
3
(2)
Chapter 3 Memory Mapping Control (S12XMMCV4)
Disabled
ES
CS1E0
2
0
Enabled
EX
CS0E1
0
1
Disabled
ST
ROMON
CS0E0
0
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