DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 261

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.5.1.1
The first example of bus timing of an external read and write access with the external wait feature disabled
is shown in
The associated supply voltage dependent timing are numbers given in
Systems designed this way rely on the internal programmable access stretching. These systems have
predictable external memory access times. The additional stretch time can be programmed up to 8 cycles
to provide longer access times.
5.5.1.2
The external wait operation is shown in this example. It can be used to exceed the amount of stretch cycles
over the programmed number in EXSTR[2:0]. The feature must be enabled by configuring at least one
CSx line for EWAIT.
If the EWAIT signal is not asserted, the number of stretch cycles is forced to a minimum of 2 cycles. If
EWAIT is asserted within the predefined time window during the access it will be strobed active and
another stretch cycle is added. If strobed inactive, the next cycle will be the last cycle before the access is
finished. EWAIT can be held asserted as long as desired to stretch the access.
An access with 1 cycle stretch by EWAIT assertion is shown in
The associated timing numbers for both operations are given in
It is recommended to use the free-running clock (ECLK) at the fastest rate (bus clock rate) to synchronize
the EWAIT input signal.
5.5.2
In emulation mode applications, the development systems use a custom PRU device to rebuild the single-
chip or expanded bus functions which are lost due to the use of the external bus with an emulator.
Accesses to a set of registers controlling the related ports in normal modes (refer to SoC section) are
directed to the external bus in emulation modes which are substituted by PRR as part of the PRU. Accesses
to these registers take a constant time of 2 cycles.
Depending on the setting of ROMON and EROMON (refer to S12X_MMC section), the program code
can be executed from internal memory or an optional external emulation memory (EMULMEM). No wait
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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Figure ‘Example 1a: Normal Expanded Mode — Read Followed by Write’
Table ‘Example 1a: Normal Expanded Mode Timing V
Table ‘Example 1a: Normal Expanded Mode Timing V
Figure ‘Example 1b: Normal Expanded Mode — Stretched Read Access’
Figure ‘Example 1b: Normal Expanded Mode — Stretched Write Access’
Table ‘Example 1b: Normal Expanded Mode Timing V
Table ‘Example 1b: Normal Expanded Mode Timing V
Emulation Modes
Example 1a: External Wait Feature Disabled
Example 1b: External Wait Feature Enabled
MC9S12XE-Family Reference Manual Rev. 1.23
DD5
DD5
DD5
DD5
= 5.0 V (EWAIT disabled)’
= 3.0 V (EWAIT disabled)’
= 5.0 V (EWAIT enabled)’
= 3.0 V (EWAIT enabled)’
Chapter 5 External Bus Interface (S12XEBIV4)
261