DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 255

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The resulting timing pattern of the external bus signals is outlined in the following tables for read, write
and interleaved read/write accesses. Three examples represent different access lengths of 1, 2, and n–1 bus
cycles. Non-shaded bold entries denote all values related to Access #0.
The following terminology is used:
5.4.2.4.1
Freescale Semiconductor
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
‘addr’ — value(ADDRx); small letters denote the logic values at the respective pins
‘x’ — Undefined output pin values
‘z’ — Tristate pins
‘?’ — Dependent on previous access (read or write); IVDx: ‘ivd’ or ‘x’; DATAx: ‘data’ or ‘z’
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
RW
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
RW
Read Access Timing
...
...
...
...
...
addr 0
high
?
MC9S12XE-Family Reference Manual Rev. 1.23
Table 5-14. Read Access (n–1 Cycles)
...
...
...
...
...
...
...
Table 5-13. Read Access (2 Cycles)
...
...
...
...
...
...
...
1
Table 5-12. Read Access (1 Cycle)
iqstat-1
acc 0
addr 0
addr 0
low
?
z
high
high
?
?
1
?
?
1
1
1
addr 0
iqstat -1
high
iqstat-1
acc 0
acc 0
z
low
low
Access #0
Access #0
Access #0
?
z
z
1
?
z
z
1
2
iqstat 0
000
addr 0
low
addr 1
data 0
x
z
high
high
z
1
z
z
1
2
2
addr 0
iqstat 0
iqstat 0
high
acc 1
ivd 0
z
000
low
low
1
x
1
z
z
z
z
Chapter 5 External Bus Interface (S12XEBIV4)
3
0000
000
data 0
low
addr 2
data 1
addr 1
x
z
high
high
Access #1
Access #1
z
1
z
1
...
...
...
...
...
...
3
3
iqstat 1
acc 2
acc 1
ivd 0
ivd 1
0000
low
low
addr 1
z
z
1
z
z
1
high
Access #1
z
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
n
acc 1
0000
ivd 0
low
z
255
...
...
...
...
...
...