DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 708

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
Read: Anytime
Write: Anytime (any value written causes PWM counter to be reset to $00).
19.3.2.13 PWM Channel Period Registers (PWMPERx)
There is a dedicated period register for each channel. The value in this register determines the period of
the associated PWM channel.
The period registers for each channel are double buffered so that if they change while the channel is
enabled, the change will NOT take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period register will go directly to the
latches as well as the buffer.
See
To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,
or SB) and multiply it by the value in the period register for that channel:
For boundary case programming values, please refer to
708
Module Base + 0x000C = PWMCNT0, 0x000D = PWMCNT1, 0x000E = PWMCNT2, 0x000F = PWMCNT3
Module Base + 0x0010 = PWMCNT4, 0x0011 = PWMCNT5, 0x0012 = PWMCNT6, 0x0013 = PWMCNT7
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur.
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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Section 19.4.2.3, “PWM Period and Duty”
W
R
The effective period ends
The counter is written (counter resets to $00)
The channel is disabled
Left aligned output (CAEx = 0)
PWMx Period = Channel Clock Period * PWMPERx Center Aligned Output (CAEx = 1)
PWMx Period = Channel Clock Period * (2 * PWMPERx)
Bit 7
0
0
7
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active period due to the double
buffering scheme.
Figure 19-14. PWM Channel Counter Registers (PWMCNTx)
0
0
6
6
MC9S12XE-Family Reference Manual , Rev. 1.23
5
0
0
5
for more information.
NOTE
NOTE
0
0
4
4
Section 19.4.2.8, “PWM Boundary
0
0
3
3
2
0
0
2
Freescale Semiconductor
0
0
1
1
Cases”.
Bit 0
0
0
0