DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 809

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3.2.17 Pulse Accumulators Count Registers (PACNT)
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on its input pin since the last reset.
When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word.
Freescale Semiconductor
Module Base + 0x0022
Module Base + 0x0023
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
PAOVF
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
PAIF
1
0
W
W
R
R
PACNT15
PACNT7
Pulse Accumulator Overflow Flag — Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000.
Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of
PACTL register is set to one.
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IOC7 input pin triggers PAIF.
Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of
PACTL register is set to one. Any access to the PACNT register will clear all the flags in this register when TFFCA
bit in register TSCR(0x0006) is set.
15
0
0
7
edge on the pulse accumulator input pin may miss the last count because the
input has to be synchronized with the bus clock first.
Reading the pulse accumulator counter registers immediately after an active
Figure 22-26. Pulse Accumulator Count Register High (PACNTH)
Figure 22-27. Pulse Accumulator Count Register Low (PACNTL)
PACNT14
PACNT6
14
0
0
6
MC9S12XE-Family Reference Manual Rev. 1.23
Table 22-21. PAFLG Field Descriptions
PACNT13
PACNT5
13
0
5
0
PACNT12
PACNT4
NOTE
12
0
0
4
Description
PACNT11
Chapter 22 Timer Module (TIM16B8CV2) Block Description
PACNT3
11
0
0
3
PACNT10
PACNT2
10
0
2
0
PACNT9
PACNT1
0
0
9
1
PACNT8
PACNT0
0
0
0
0
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