DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 475

BOARD DEMO FOR MC9S12XEP100

DEMO9S12XEP100

Manufacturer Part Number
DEMO9S12XEP100
Description
BOARD DEMO FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of DEMO9S12XEP100

Contents
Board, Cables, CD
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
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Part Number:
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Manufacturer:
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11.3.2
This section describes in address order all the S12XECRG registers and their individual bits.
11.3.2.1
The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range.
Read: Anytime
Write: Anytime except if PLLSEL = 1
The VCOFRQ[1:0] bit are used to configure the VCO gain for optimal stability and lock time. For correct
IPLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in
IPLL (no locking and/or insufficient stability).
Freescale Semiconductor
Module Base + 0x0000
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
R
f VCO
f PLL
f BUS
Register Descriptions
=
=
S12XECRG Synthesizer Register (SYNR)
0
=
7
VCOFRQ[1:0]
Write to this register initializes the lock detector bit.
f
Clock) must not exceed the specified maximum. If POSTDIV = $00 then
f
----------------------------------- -
2 POSTDIV
f PLL
------------ -
VCO
PLL
2 f OSC
×
2
×
f VCO
is same as f
must be within the specified VCO frequency lock range. F.
Table
×
0
6
Figure 11-3. S12XECRG Synthesizer Register (SYNR)
(
------------------------------------ -
(
SYNDIV
REFDIV
11-2. Setting the VCOFRQ[1:0] bits wrong can result in a non functional
Table 11-2. VCO Clock Frequency Selection
VCO
MC9S12XE-Family Reference Manual Rev. 1.23
VCOCLK Frequency Ranges
32MHz <= f
80MHz < f
48MHz < f
+
+
(divide by one).
1
1
5
0
)
)
Reserved
VCO
VCO
VCO
<= 80MHz
<= 120MHz
<= 48MHz
NOTE
NOTE
0
4
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
0
3
VCOFRQ[1:0]
SYNDIV[5:0]
00
01
10
11
2
0
BUS
(Bus
0
1
0
0
475

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