DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 2

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To provide the most up-to-date information, the document revision on the World Wide Web is the most
current. A printed copy may be an earlier revision. To verif, refer to: http://freescale.com/
This document contains information for the complete S12XE-Family and thus includes a set of separate
FTM module sections to cover the whole family. A full list of family members and options is included in
the appendices.
This document contains information for all constituent modules, with the exception of the S12X CPU. For
S12X CPU information please refer to CPU12XV2 in the CPU12/CPU12X Reference Manual.
Revision History
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Dec, 2008
Aug, 2009
May, 2010
Sep, 2008
Sep, 2010
Apr, 2010
May,2008
Jul, 2008
Date
Revision
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
Figure B-3
Added LVR minimum assert level
Enhanced RESET pin description.
IIC register name corrected
Corrected D-Flash size reference for XEG128
Changed module revision history tables to a unified format
Corrected corrupted formats
Added Module Run Idd Values
Added 3.3V expansion bus timing
Corrected NVM timing parameters
Changed IIC SCL Divider note
Updated NVM timing parameter section for brownout case
Specified time delay from RESET to start of CPU code execution
Added NVM patch Part IDs
Enhanced ECT GPIO / timer function transitioning description
Updated 208MAPBGA thermal parameters
Revised TIM flag clearing procedure
Corrected CRG register address
Added maskset identifier suffix for ATMC fab
Fixed typos
Added 208MAPBGA disclaimer
Added VREAPI to PT5. Added LVR Note to electricals.
Updates to TIM/ECT/XGATE/SCI/MSCAN (see embedded rev. history)
FTM section (see FTM revision history)
PIM section (see PIM revision history)
ECT and TIM sections (see ECT, TIM revision history tables)
BDM Alternate clock source defined in device overview
Added S12XEG256 option. Updated MSCAN section
Θ1 value corrected.
Description