DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 323

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.2.8
Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG
module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare
registers, two data bus compare registers, two data bus mask registers and a control register).
Comparators B and D consist of four register bytes (three address bus compare registers and a control
register).
Each set of comparator registers is accessible in the same 8-byte window of the register address map and
can be accessed using the COMRV bits in the DBGC1 register. If the Comparators B or D are accessed
through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with
data bus and data bus masking read as zero and cannot be written. Furthermore the control registers for
comparators B and D differ from those of comparators A and C.
8.3.2.8.1
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Read: Anytime. See
Freescale Semiconductor
Address: 0x0028
Address: 0x0028
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
0x002A
0x002B
0x002C
0x002D
0x002E
0x0028
0x0029
0x002F
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
W
R
R
SZE
Comparator Register Descriptions
0
0
0
7
7
Debug Comparator Control Register (DBGXCTL)
Figure 8-13. Debug Comparator Control Register (Comparators A and C)
Figure 8-14. Debug Comparator Control Register (Comparators B and D)
DATA HIGH COMPARATOR
DATA LOW COMPARATOR
Table 8-29
= Unimplemented or Reserved
ADDRESS MEDIUM
DATA HIGH MASK
DATA LOW MASK
ADDRESS HIGH
ADDRESS LOW
NDB
SZ
0
0
6
6
CONTROL
MC9S12XE-Family Reference Manual Rev. 1.23
for visible register encoding.
Table 8-28. Comparator Register Layout
TAG
TAG
5
0
5
0
BRK
BRK
0
0
4
4
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
RW
RW
0
0
3
3
Chapter 8 S12X Debug (S12XDBGV3) Module
RWE
RWE
2
0
2
0
Comparator A and C only
Comparator A and C only
Comparator A and C only
Comparator A and C only
Comparators A,B,C,D
Comparators A,B,C,D
Comparators A,B,C,D
Comparators A,B,C,D
SRC
SRC
0
0
1
1
COMPE
COMPE
0
0
0
0
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