DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 499

BOARD DEMO FOR MC9S12XEP100

DEMO9S12XEP100

Manufacturer Part Number
DEMO9S12XEP100
Description
BOARD DEMO FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of DEMO9S12XEP100

Contents
Board, Cables, CD
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DEMO9S12XEP100
Manufacturer:
PANASONIC
Quantity:
46 000
Part Number:
DEMO9S12XEP100
Manufacturer:
Freescale Semiconductor
Quantity:
135
S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check
indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50
check windows the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts
using Self-Clock Mode.
Figure 11-22
and when the RESET pin is held low.
11.6
The interrupts/reset vectors requested by the S12XECRG are listed in
specification for related vector addresses and priorities.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Interrupts
and
Figure 11-23
Internal RESET
Internal RESET
RESET
Internal POR
RESET
Internal POR
Figure 11-22. RESET Pin Tied to V
Interrupt Source
Real time interrupt
LOCK interrupt
SCM interrupt
Figure 11-23. RESET Pin Held Low Externally
show the power-up sequence for cases when the RESET pin is tied to V
MC9S12XE-Family Reference Manual Rev. 1.23
Table 11-18. S12XECRG Interrupt Vectors
Mask
Clock Quality Check
(no Self-Clock Mode)
Clock Quality Check
(no Self Clock Mode)
CCR
I bit
I bit
I bit
128 SYSCLK
) (
) (
) (
128 SYSCLK
) (
) (
) (
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
64 SYSCLK
64 SYSCLK
DD
(by a Pull-up Resistor)
CRGINT (LOCKIE)
CRGINT (SCMIE)
CRGINT (RTIE)
Local Enable
Table
11-18. Refer to MCU
DD
499

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