DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 58

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 1 Device Overview MC9S12XE-Family
58
Function 1
PAD[31:16] AN[31:16]
PAD[15:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
RESET
PB[7:1]
PC[7:0]
PD[7:0]
PA[7:0]
EXTAL
BKGD
Name
TEST
XTAL
PB0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
PF7
PF6
PF5
PF4
PF3
Pin
ADDR[15:8] IVD[15:8]
Function 2
DATA[15:8]
ADDR[7:1]
DATA[7:0]
AN[15:0]
ECLKX2
ADDR0
LSTRB
MODC
TAGHI
Name
ECLK
RXD3
XIRQ
TXD3
SCL0
SDA0
R/W
CS3
IRQ
Pin
RE
—
—
—
—
Function 3
IVD[7:0]
XCLKS
MODB
MODA
Name
UDS
LDS
Pin
WE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 1-10. Signal Properties Summary (Sheet 1 of 4)
MC9S12XE-Family Reference Manual , Rev. 1.23
Function 4
EROMCTL
TAGLO
Name
Pin
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Function 5
Name
Pin
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Supply
V
V
Power
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDPLL
DDPLL
N.A.
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDA
DDA
RESET pin
Always on
PER0AD1
PER1AD1
PER0AD0
PER1AD0
PERF/
PERF/
PERF/
PERF/
PERF/
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
PUCR
CTRL
pin is low: down
pin is low: down
PPSF
PPSF
PPSF
PPSF
PPSF
While RESET
While RESET
Internal Pull
NA
NA
Resistor
PULLUP
Disabled Port AD inputs of ATD1,
Disabled Port AD inputs of ATD0,
Disabled Port A I/O, address bus,
Disabled Port B I/O, address bus,
Disabled Port B I/O, address bus,
Disabled Port C I/O, data bus
Disabled Port D I/O, data bus
DOWN Test input
Reset
State
NA
NA
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Oscillator pins
External reset
Background debug
analog inputs of ATD1
analog inputs of ATD0
internal visibility data
internal visibility data
upper data strobe
Port E I/O, system clock
output, clock select
Port E I/O, tag high, mode
input
Port E I/O, read enable,
mode input, tag low input
Port E I/O, bus clock output
Port E I/O, low byte data
strobe, EROMON control
Port E I/O, read/write
Port E Input, maskable
interrupt
Port E input, non-maskable
interrupt
Port F I/O, interrupt, TXD of
SCI3
Port F I/O, interrupt, RXD of
SCI3
Port F I/O, interrupt, SCL of
IIC0
Port F I/O, interrupt, SDA of
IIC0
Port F I/O, interrupt, chip
select 3
Freescale Semiconductor
Description