DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 376

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 XGATE (S12XGATEV3)
Section for information on how to select priority levels for XGATE threads. Low priority threads (interrupt
levels 1 to 3) can be interrupted by high priority threads (interrupt levels 4 to 7). High priority threads are
not interruptible. The register content of an interrupted thread is maintained and restored by the XGATE
hardware.
To signal the completion of a task the XGATE is able to send interrupts to the S12X_CPU. Each XGATE
channel has its own interrupt vector. Refer to the S12X_INT Section for detailed information.
The XGATE module also provides a set of hardware semaphores which are necessary to ensure data
consistency whenever RAM locations or peripherals are shared with the S12X_CPU.
The following sections describe the components of the XGATE module in further detail.
10.4.1
The RISC core is a 16 bit processor with an instruction set that is well suited for data transfers, bit
manipulations, and simple arithmetic operations (see
It is able to access the MCU’s internal memories and peripherals without blocking these resources from
the S12X_CPU
will be stalled until the resource becomes available again.
The XGATE offers a high access rate to the MCU’s internal RAM. Depending on the bus load, the RISC
core can perform up to two RAM accesses per S12X_CPU bus cycle.
Bus accesses to peripheral registers or flash are slower. A transfer rate of one bus access per S12X_CPU
cycle can not be exceeded.
The XGATE module is intended to execute short interrupt service routines that are triggered by peripheral
modules or by software.
10.4.2
1. With the exception of PRR registers (see Section “S12X_MMC”).
376
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indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
XGATE RISC Core
Programmer’s Model
1
. Whenever the S12X_CPU and the RISC core access the same resource, the RISC core
15
15
15
15
15
15
15
15
Register Block
MC9S12XE-Family Reference Manual , Rev. 1.23
R7
R0 = 0
R6
R5
R4
R3
R2
R1
Figure 10-22. Programmer’s Model
(Stack Pointer)
(Data Pointer)
0
0
0
0
0
0
0
0
Section 10.8, “Instruction
15
1
Program Counter
PC
Condition
Register
N Z
3 2
Code
Set”).
V C
1 0
0
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