DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 371

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3.1.11 XGATE Condition Code Register (XGCCR)
The XGCCR register
Module Base +0x001D
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Freescale Semiconductor
XGSEMM[7:0]
XGSEM[7:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Reset
Field
15–8
Field
XGN
XGV
XGC
XGZ
7–0
3
2
1
0
W
R
0
0
Semaphore Mask — These bits control the write access to the XGSEM bits.
Read:
These bits will always read "0".
Write:
0 Disable write access to the XGSEM in the same bus cycle
1 Enable write access to the XGSEM in the same bus cycle
Semaphore Bits — These bits indicate whether a semaphore is locked by the S12X_CPU. A semaphore can
be attempted to be set by writing a "1" to the XGSEM bit and to the corresponding XGSEMM bit in the same
write access. Only unlocked semaphores can be set. A semaphore can be cleared by writing a "0" to the
XGSEM bit and a "1" to the corresponding XGSEMM bit in the same write access.
Read:
0 Semaphore is unlocked or locked by the RISC core
1 Semaphore is locked by the S12X_CPU
Write:
0 Clear semaphore if it was locked by the S12X_CPU
1 Attempt to lock semaphore by the S12X_CPU
7
Sign Flag — The RISC core’s Sign flag
Zero Flag — The RISC core’s Zero flag
Overflow Flag — The RISC core’s Overflow flag
Carry Flag — The RISC core’s Carry flag
= Unimplemented or Reserved
(Figure
Figure 10-13. XGATE Condition Code Register (XGCCR)
0
0
6
10-13) provides access to the RISC core’s condition code register.
MC9S12XE-Family Reference Manual Rev. 1.23
Table 10-12. XGSEM Field Descriptions
Table 10-13. XGCCR Field Descriptions
0
0
5
0
0
4
Description
Description
XGN
0
3
XGZ
0
2
Chapter 10 XGATE (S12XGATEV3)
XGV
0
1
XGC
0
0
371