DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 378

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 XGATE (S12XGATEV3)
10.4.4
The XGATE module offers a set of eight hardware semaphores. These semaphores provide a mechanism
to protect system resources that are shared between two concurrent threads of program execution; one
thread running on the S12X_CPU and one running on the XGATE RISC core.
Each semaphore can only be in one of the three states: “Unlocked”, “Locked by S12X_CPU”, and “Locked
by XGATE”. The S12X_CPU can check and change a semaphore’s state through the XGATE semaphore
register (XGSEM, see
this through its SSEM and CSEM instructions.
IFigure 10-24
378
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
XGVBR
+$0000
+$0024
+$0028
+$002C
+$0030
+$01E0
Semaphores
illustrates the valid state transitions.
Channel $09 Initial Program Counter
Channel $09 Initial Data Pointer
Channel $0A Initial Program Counter
Channel $0A Initial Data Pointer
Channel $0B Initial Program Counter
Channel $0B Initial Data Pointer
Channel $0C Initial Program Counter
Channel $0C Initial Data Pointer
Channel $78 Initial Program Counter
Channel $78 Initial Data Pointer
Section 10.3.1.10, “XGATE Semaphore Register
MC9S12XE-Family Reference Manual , Rev. 1.23
unused
Figure 10-23. XGATE Vector Block
(XGSEM)”). The RISC core does
Code
Data
Code
Data
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