DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 191

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3
Memory Mapping Control (S12XMMCV4)
3.1
This section describes the functionality of the module mapping control (MMC) sub-block of the S12X
platform. The block diagram of the MMC is shown in
The MMC module controls the multi-master priority accesses, the selection of internal resources and
external space. Internal buses, including internal memories and peripherals, are controlled in this module.
The local address space for each master is translated to a global memory space.
Freescale Semiconductor
Revision
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Number
V04.04
V04.05
V04.06
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Introduction
Revision Date
15 Nov 2006
26 Oct 2005
26 Jul 2006
3.4.2.4/3-216
MC9S12XE-Family Reference Manual , Rev. 1.23
Sections
Affected
Table 3-1. Revision History
- Reorganization of MEMCTL0 register bits.
- Updated XGATE Memory Map
- Adding AUTOSAR Compliance concerning illegal CPU accesses
Figure
3-1.
Description of Changes
191