DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 768

BOARD DEMO FOR MC9S12XEP100

DEMO9S12XEP100

Manufacturer Part Number
DEMO9S12XEP100
Description
BOARD DEMO FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of DEMO9S12XEP100

Contents
Board, Cables, CD
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Quantity
Price
Part Number:
DEMO9S12XEP100
Manufacturer:
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Quantity:
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Part Number:
DEMO9S12XEP100
Manufacturer:
Freescale Semiconductor
Quantity:
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Chapter 21 Serial Peripheral Interface (S12SPIV5)
21.3.2.2
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
768
Module Base +0x0001
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
LSBFE
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
SSOE
Field
1
0
W
R
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by
asserting the SSOE as shown in
progress and force the SPI system into idle state.
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and
writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
SPI Control Register 2 (SPICR2)
0
0
7
MODFEN
= Unimplemented or Reserved
0
0
1
1
XFRW
0
6
Table 21-2. SPICR1 Field Descriptions (continued)
SSOE
Figure 21-4. SPI Control Register 2 (SPICR2)
MC9S12XE-Family Reference Manual , Rev. 1.23
0
1
0
1
Table 21-3. SS Input / Output Selection
5
0
0
Table
SS input with MODF feature
21-3. In master mode, a change of this bit will abort a transmission in
SS is slave select output
MODFEN
SS not used by SPI
SS not used by SPI
Master Mode
0
4
Description
BIDIROE
0
3
2
0
0
Slave Mode
SS input
SS input
SS input
SS input
SPISWAI
Freescale Semiconductor
0
1
SPC0
0
0

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