DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 765

BOARD DEMO FOR MC9S12XEP100

DEMO9S12XEP100

Manufacturer Part Number
DEMO9S12XEP100
Description
BOARD DEMO FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of DEMO9S12XEP100

Contents
Board, Cables, CD
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DEMO9S12XEP100
Manufacturer:
PANASONIC
Quantity:
46 000
Part Number:
DEMO9S12XEP100
Manufacturer:
Freescale Semiconductor
Quantity:
135
21.2
This section lists the name and description of all ports including inputs and outputs that do, or may, connect
off chip. The SPI module has a total of four external pins.
21.2.1
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data
when it is configured as slave.
21.2.2
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Bus Clock
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Interrupt
Request
SPI
External Signal Description
MOSI — Master Out/Slave In Pin
MISO — Master In/Slave Out Pin
SPPR
SPI
SPI Baud Rate Register
Prescaler
SPI Control Register 1
SPI Control Register 2
Baud Rate Generator
SPI Status Register
SPI Data Register
Interrupt Control
SPIF
3
SPR
MODF
Clock Select
Counter
MC9S12XE-Family Reference Manual Rev. 1.23
SPTEF
3
Figure 21-1. SPI Block Diagram
Baud Rate
LSBFE=1
LSBFE=0
Control
Control
Master
Slave
Master Baud Rate
Slave Baud Rate
MSB
2
2
Shifter
LSBFE=1
LSBFE=0
LSBFE=0
LSBFE=1
CPOL
Clock
Shift
Phase +
Polarity
Control
Phase +
Polarity
Control
Chapter 21 Serial Peripheral Interface (S12SPIV5)
LSB
CPHA
BIDIROE
SPC0
Sample
Clock
Data Out
SCK In
SCK Out
Data In
Control
Logic
Port
MOSI
SCK
SS
765

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