DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 830

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 23 Voltage Regulator (S12VREGL3V3V1)
The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency
is desired.
See
It is possible to generate with the API a waveform at an external pin by enabling the API by setting APIFE
and enabling the external access with setting APIEA. By setting APIES the waveform can be selected. If
APIES is set, then at the external pin a clock is visible with 2 times the selected API Period
If APIES is not set, then at the external pin will be a high pulse at the end of every selected period with the
size of half of the min period
23.4.9
This section describes how VREG_3V3 controls the reset of the MCU.The reset values of registers and
signals are provided in
listed in
23.4.10 Description of Reset Operation
23.4.10.1 Power-On Reset (POR)
During chip power-up the digital core may not work if its supply voltage V
deassertion level (V
is kept high until V
The power-on reset is active in all operation modes of VREG_3V3.
23.4.10.2 Low-Voltage Reset (LVR)
For details on low-voltage reset, see
23.4.11 Interrupts
This section describes all interrupts originated by VREG_3V3.
The interrupt vectors requested by VREG_3V3 are listed in
priorities are defined at MCU level.
830
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Table 23-7
Table
Resets
23-12.
The first period after enabling the counter by APIFE might be reduced by
API start up delay t
if VREG_3V3 is in Shutdown Mode.
for the trimming effect of APITR.
DD
PORD
exceeds V
Section 23.3, “Memory Map and Register
). Therefore, signal POR, which forces the other blocks of the device into reset,
Low-voltage reset
Power-on reset
Reset Source
(Table
MC9S12XE-Family Reference Manual , Rev. 1.23
PORD
sdel
23-9). See device level specification for connectivity.
Section 23.4.5, “Low-Voltage Reset
. The API internal RC oscillator clock is not available
. The MCU will run the start-up sequence after POR deassertion.
Table 23-12. Reset Sources
Available only in Full Performance Mode
NOTE
Local Enable
Always active
Table
Definition”. Possible reset sources are
23-13. Vector addresses and interrupt
(LVR)”.
DD
is below the POR
Freescale Semiconductor
(Table
23-9).