DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 491

BOARD DEMO FOR MC9S12XEP100

DEMO9S12XEP100

Manufacturer Part Number
DEMO9S12XEP100
Description
BOARD DEMO FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of DEMO9S12XEP100

Contents
Board, Cables, CD
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DEMO9S12XEP100
Manufacturer:
PANASONIC
Quantity:
46 000
Part Number:
DEMO9S12XEP100
Manufacturer:
Freescale Semiconductor
Quantity:
135
11.4.1.3
If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block
generates a clock monitor fail event. The S12XECRG then asserts self clock mode or generates a system
reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is
detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by
the CME control bit.
11.4.1.4
The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker
provides a more accurate check in addition to the clock monitor.
A clock quality check is triggered by any of the following events:
A time window of 50000 PLLCLK cycles
A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that
osc ok immediately terminates the current check window. See
1. IPLL is running at self clock mode frequency f
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Power on reset (POR)
Low voltage reset (LVR)
Wake-up from Full Stop Mode (exit full stop)
Clock Monitor fail indication (CM fail)
Clock Monitor (CM)
Clock Quality Checker
OSCCLK
PLLCLK
MC9S12XE-Family Reference Manual Rev. 1.23
1
1
Figure 11-17. Check Window Example
2
2
SCM
3
1
.
is called check window.
4
3
CHECK WINDOW
5
4095
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
OSC OK
4096
Figure 11-17
49999
as an example.
50000
491

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