DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 239

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.1.8
Read: Anytime
Write: Anytime
4.3.1.9
Read: Anytime
Write: Anytime
Freescale Semiconductor
Address: Module Base + 0x0008
Address: Module Base + 0x0009
LOW_ADDR[
LOW_ADDR[
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
18:11]
Field
Field
Field
10:3]
7–0
7–0
WP
7
W
W
R
R
WP
MPU Descriptor Register 2 (MPUDESC2)
MPU Descriptor Register 3 (MPUDESC3)
Memory range lower boundary address bits — The LOW_ADDR[18:11] bits represent bits [18:11] of the
global memory address that is used as the lower boundary for the described memory range.
Memory range lower boundary address bits — The LOW_ADDR[10:3] bits represent bits [10:3] of the global
memory address that is used as the lower boundary for the described memory range.
Write-Protect bit — The WP bit causes the described memory range to be treated as write-protected. If this
bit is set every attempt to write in the described memory range causes an access violation.
0
0
7
7
NEX
0
0
6
6
Figure 4-10. MPU Descriptor Register 2 (MPUDESC2)
Figure 4-11. MPU Descriptor Register 3 (MPUDESC3)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 4-10. MPUDESC2 Field Descriptions
Table 4-11. MPUDESC3 Field Descriptions
Table 4-9. MPUDESC1 Field Descriptions
5
0
5
0
0
LOW_ADDR[10:3]
0
0
0
4
4
Description
Description
Description
0
1
3
3
Chapter 4 Memory Protection Unit (S12XMPUV1)
HIGH_ADDR[22:19]
2
0
2
1
0
1
1
1
0
1
0
0
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