DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 171

BOARD DEMO FOR MC9S12XEP100

DEMO9S12XEP100

Manufacturer Part Number
DEMO9S12XEP100
Description
BOARD DEMO FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of DEMO9S12XEP100

Contents
Board, Cables, CD
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DEMO9S12XEP100
Manufacturer:
PANASONIC
Quantity:
46 000
Part Number:
DEMO9S12XEP100
Manufacturer:
Freescale Semiconductor
Quantity:
135
1. Read: Always reads 0x00
1. Read: Anytime.
2.3.91
2.3.92
Freescale Semiconductor
Address 0x036E
Address 0x036F
PTRRR
PTRRR
Write: Unimplemented
Write: Anytime.
PPSR
Field
Field
Reset
Reset
7-0
7
6
W
W
R
R
Port R pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
PTRRR7
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC7 is available on PP7
0 TIMIOC7 is available on PR7
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC6 is available on PP6
0 TIMIOC6 is available on PR6
PIM Reserved Register
Port R Routing Register (PTRRR)
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
PTRRR6
0
0
0
6
6
Table 2-87. PTR Routing Register Field Descriptions
Figure 2-90. Port R Routing Register (PTRRR)
Table 2-86. PPSR Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
PTRRR5
Figure 2-89. PIM Reserved Register
0
0
0
5
5
PTRRR4
0
0
0
4
4
Description
Description
PTRRR3
3
0
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
PTRRR2
0
0
0
2
2
Access: User read/write
PTRRR1
0
0
0
1
1
Access: User read
PTRRR0
0
0
0
0
0
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