MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1020

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Bus Interface
17.3.2.20 PCI Bus Arbiter Configuration Register (PBACR)
The PCI bus arbiter configuration register is used to determine the configuration of the PCI bus arbiter.
Offset 0x46
17.4
This section describes the functionality of the PCI interface.
17.4.1
PCI bus arbitration is access-based. Bus masters must arbitrate for each access performed on the bus. The
PCI bus uses a central arbitration scheme where each master has its own unique request (REQ) output and
17-42
Reset
W
R PAD
11–7
Bits Name
6–2 PBMP PCI bus master priorities. Determines arbitration priority given to different masters on the PCI bus. Bit 6
15
14
13
12
1
0
15
PBMD PCI broken master disable. Determines if the device ignores the bus requests of an initiator that requests
Functional Description
PAD PCI arbiter disable. Determines if the device is the PCI arbiter on the PCI bus or not. The reset state is
PM
DP
—
—
—
PCI Bus Arbitration
PM
14
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
determined by the inverse of the cfg_pci n _arb configuration input signal when reset is released.
0 Device is the PCI arbiter.
1 Device is not the PCI arbiter. Device presents its request on PCI_REQ0 to the external arbiter and
Parking mode. controls which device receives the bus grant when there are no outstanding bus requests
and the bus is idle.
0 The bus is parked on the last device to use the bus.
1 The bus is parked on the device.
Reserved
the bus for an excessive period without using the bus.
0 An initiator that requests the bus and receives the grant must begin using the bus within 16 PCI clock
1 No requests are ignored.
Reserved
corresponds to the priority of the master sourcing PCI_REQ0; bit 2 corresponds to the priority of the
master sourcing PCI_REQ4.
0 Master n is low priority.
1 Master n is high priority.
Reserved
Device priority. Determines this device’s arbitration priority.
0 Device is low priority.
1 Device is high priority.
receives its grant on PCI_GNT0.
periods after the bus becomes idle or else its request is subsequently ignored.
Table 17-46. PCI Bus Arbiter Configuration Register Field Descriptions
—
13
PBMD
Figure 17-47. PCI Bus Arbiter Configuration Register
12
11
—
All zeros
Description
7
6
PBMP
Freescale Semiconductor
2
Access: Mixed
—
1
DP
0