MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1199

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

In addition to these registers, the interrupt control provides four pairs of mask registers that can be used to
monitor message, interprocessor, timer, and external interrupts. See
Mask Registers (PMMRs),” on page
20.3.2
This section describes the performance monitor control registers in detail.
20.3.2.1
The performance monitor global control register (PMGC0), shown in
to control all PMCs.
Table 20-2
Freescale Semiconductor
Address Offset
Offset 0xE_1000
Reset
0xE_10A4
0xE_10A8
(in Hex)
3–31
Bits
0
1
2
W
R
FAC PMIE FCECE
(DISCOUNT)
0
describes PMGC0 fields.
Control Registers
FCECE
Name
PMIE
Performance Monitor Global Control Register (PMGC0)
FAC
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
1
PMLCB9—Performance monitor local control register B9
PMC9—Performance monitor counter 9
Figure 20-2. Performance Monitor Global Control Register (PMGC0)
2
Freeze all counters.
0 PMCs are incremented (if permitted by other PMGC0/PMLC bits).
1 PMCs are not incremented. Set by hardware when an interrupt is signalled and FCECE =1.
Performance monitor interrupt enable. Interrupts are caused by PMC overflows.
0 Interrupts are disabled.
1 Interrupts are enabled and occur when an enabled condition or event occurs.
Freeze counters on enabled condition or event. An enabled condition or event is defined as:
The use of the trigger and freeze counter conditions depends on the enabled condition.
0 PMCs can be incremented (if permitted by other control bits).
1 PMCs can be incremented (if permitted by other control bits) only until an enabled condition
Reserved
or event occurs, at which time PMGC0[FAC] is set. It is up to software to clear FAC.
Table 20-1. Control Register Memory Map (continued)
3
The msb = 1 in PMC n and PMLCA n [CE] = 1.
Table 20-2. PMGC0 Field Descriptions
10-32.
Register
All zeros
Description
—
Section 10.3.4, “Performance Monitor
Figure
Access
R/W
R/W
20-2, is a 32-bit register used
0x0000_0000
0x0000_0000
Reset
Device Performance Monitor
Access: Read/Write
20.3.3.1/20-10
Section/Page
20.3.2.2/20-6
20-5
31