MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 173

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

4.4.3.7
The CPU boot configuration input, shown in
is sampled low at reset, the e500 core is prevented from fetching boot code until configuration by an
external master is complete. The external master frees the CPU to boot by setting EEBPCR[CPU_EN] in
the ECM CCB port configuration register (EEBPCR). See
Register (EEBPCR),”
Freescale Semiconductor
TSEC3_TXD[6:4]
Default (111)
Functional
Signal
CPU Boot Configuration
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reset Configuration
cfg_IO_ports[0:2]
cfg_IO_ports[0:2]
for more information.
Name
Table 4-14. I/O Port Selection
(Binary)
Value
000
001
010
011
100
101
110
111
Table
All three PCI Express ports powered down
Reserved
PCI Express port 1active
PCI Express ports 2 and 3 powered down
PCI Express 1:
RX lane[0:3] -> SD1_RX[0:3],
TX lane[0:3] -> SD1_TX[0:3]
Reserved
PCI Express ports 1 and 2 active
PCI Express port 3 powered down
PCI Express 1:
RX lane[0:3] -> SD1_RX[0:3],
TX lane[0:3] -> SD1_TX[0:3]
PCI Express 2:
RX lane[0:3] -> SD1_RX[4:7],
TX lane[0:3] -> SD1_TX[4:7]
Reserved
All three PCI Express ports active
PCI Express 1:
RX lane[0:3] -> SD1_RX[0:3],
TX lane[0:3] -> SD1_TX[0:3]
PCI Express 2:
RX lane[0:3] -> SD1_RX[4:7],
TX lane[0:3] -> SD1_TX[4:7]
PCI Express 3:
RX lane[0] -> SD2_RX[0],
TX lane[0] -> SD2_TX[0]
Reserved
4-15, specifies the boot configuration mode. If LA27
Section 8.2.1.2, “ECM CCB Port Configuration
Meaning
Reset, Clocking, and Initialization
4-15