MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 545

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.5.7
The RNG EU go is a writable location but serves no function in the RNG. It is documented for the sake of
consistency with the other EUs.
12.4.5.8
RNG uses an output FIFO to collect periodically sampled random 64-bit-words, with the intent that
random data always be available for reading. The FIFO is multiple-addressed, but those multiple addresses
point only to the appropriate end of the output FIFO. A read from anywhere in the RNG FIFO address
space causes a 64-bit-word to be popped off of the RNG output FIFO. Underflows caused by reading or
writing the RNG output FIFO are reflected in the RNG interrupt status register. Also, a write to the RNG
output FIFO space will be reflected as an addressing error in the RNG interrupt status register.
12.4.6
This section contains details about the advanced encryption standard execution unit (AESU), including
modes of operation, status and control registers, and FIFOs.
Most of the registers described here are not normally be accessed by the host. They are documented here
mainly for debug purposes. In typical operation, the ASEU is used through channel-controlled access,
which means that most reads and writes of ASEU registers are directed by the SEC channels. Driver
software performs host-controlled register accesses on only a few registers for initial configuration and
error handling.
12.4.6.1
The AESU mode register, shown in
The mode register is cleared when the AESU is reset or re-initialized. Setting a reserved mode bit generates
a data error. If the mode register is modified during processing, a context error is generated.
Freescale Semiconductor
Address RNG 0x3_A050
Address AESU 0x3_4000
Reset
Reset
W
R
W
R
0
0
Advanced Encryption Standard Execution Unit (AESU)
RNG EU Go Register (RNGEUG)
RNG FIFO
AESU Mode Register (AESUMR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
Figure 12-47. AESU Mode Register
Figure 12-46. RNG EU Go Register
Figure
50
12-47, contains 7 bits which are used to program the AESU.
51
SCM
52
All zeros
All zeros
53
—
54
—
55
56
ECM
57
FM
58
IM RDK
59
Security Engine (SEC) 2.1
60
Access: Read/write
Access: Write-only
61
CM
62
12-67
ED
63
63