MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1271

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
0x2_0E4C
0x2_0E50
0x2_0E54
0x2_0E58
0x148
0x10C
0x11C
0x13C
0x17C
0x18C
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x130
0x134
0x138
0x140
0x144
0x180
0x184
0x188
0x190
0x194
0x198
Offset
–
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
L2ERRATTR—L2 error attributes capture register
L2ERRADDRH—L2 error address capture register high
L2ERRADDRL—L2 error address capture register low
L2ERRCTL—L2 error control register
MR0—DMA 0 mode register
SR0—DMA 0 status register
ECLNDAR0—DMA 0 current link descriptor extended
address register
CLNDAR0—DMA 0 current link descriptor address register
SATR0—DMA 0 source attributes register
SAR0—DMA 0 source address register
DATR0—DMA 0 destination attributes register
DAR0—DMA 0 destination address register
BCR0—DMA 0 byte count register
ENLNDAR0—DMA 0 next link descriptor extended address
register
NLNDAR0—DMA 0 next link descriptor address register
ECLSDAR0—DMA 0 current list descriptor extended address
register
CLSDAR0—DMA 0 current list descriptor address register
ENLSDAR0—DMA 0 next list descriptor extended address
register
NLSDAR0—DMA 0 next list descriptor address register
SSR0—DMA 0 source stride register
DSR0—DMA 0 destination stride register
Reserved
MR1—DMA 1 mode register
SR1—DMA 1 status register
ECLNDAR1—DMA 1 current link descriptor extended
address register
CLNDAR1—DMA 1 current link descriptor address register
SATR1—DMA 1 source attributes register
SAR1—DMA 1 source address register
DATR1—DMA 1 destination attributes register
DMA Controller Block Base Address: 0x2_1000
Table B-1. Memory Map (continued)
Register
DMA Registers
Complete List of Configuration, Control, and Status Registers
Access
Mixed
Mixed
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
16.3.1.10/16-21
16.3.1.10/16-21
16.3.1.11/16-22
16.3.1.11/16-22
16.3.1.12/16-22
16.3.1.13/16-23
16.3.1.1/16-10
16.3.1.2/16-12
16.3.1.3/16-13
16.3.1.3/16-13
16.3.1.4/16-15
16.3.1.5/16-16
16.3.1.6/16-17
16.3.1.7/16-18
16.3.1.8/16-19
16.3.1.9/16-19
16.3.1.9/16-19
16.3.1.1/16-10
16.3.1.2/16-12
16.3.1.3/16-13
16.3.1.3/16-13
16.3.1.4/16-15
16.3.1.5/16-16
16.3.1.6/16-17
Section/Page
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
7.3.1.4.2/7-20
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B-13