MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 795

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
carrier, the eTSEC simply waits until the end of the carrier event and the timing of IPG before it honors
the request.
If packet transmission attempts experience collisions, the eTSEC outputs the jam sequence and waits some
amount of time before retrying the packet. This amount of time is determined by a controlled
randomization process called truncated binary exponential back-off. The amount of time is an integer
number of slot times. The number of slot times to delay before the nth retransmission attempt is chosen as
a uniformly-distributed random integer r in the range:
0 ≤ r ≤ 2
k
, where k = min(n,10).
So after the first collision, the eTSEC backs off either 0 or 1 slot times. After the fifth collision, the eTSEC
backs off between 0 and 32 slot times. After the tenth collision, the maximum number of slot times to back
off is 1024. This can be adjusted via the half-duplex register. An alternate truncation point, such as 7 for
instance, can be programmed. On average, the MAC is more aggressive after seven collisions than other
stations on the network.
15.5.3.4.4
Controlling Packet Flow
Packet flow can be dealt with in a number of ways within eTSEC. A default retransmit attempt limit of 15
can be reduced using the half-duplex register. The slot time or collision window can be used to gate the
retry window and possibly reduce the amount of transmit buffering within the system. The slot time for
10/100 Mbps is 512 bit times. Because the slot time begins at the beginning of the packet (including
preamble), the end occurs around the 56th byte of the frame data. Slot time in 1000-Mbps mode is not
supported.
Full-duplex flow control is provided for in IEEE 802.3x. Currently the standard does not address flow
control in half-duplex environments. Common in the industry, however, is the concept of back pressure.
The eTSEC implements the optional back pressure mechanism using the raise carrier method. If the system
receive logic wishes to stop the reception of packets in a network-friendly way, transmit half-duplex flow
control (THDF) is set (TCTRL[THDF]). If the medium is idle, the eTSEC raises carrier by transmitting
preamble. Other stations on the half-duplex network then defer to the carrier.
In the event the preamble transmission happens to cause a collision, the eTSEC ensures the minimum
96-bit presence on the wire, then drops preamble and waits a back-off time depending on the value of the
back-pressure-no-back-off configuration bit HAFDUP[BP No BackOff]. These
transmitting-preamble-for-back pressure collisions are not counted. If HAFDUP[BP No BackOff] is set,
the eTSEC waits an inter-packet gap before resuming the transmission of preamble following the collision
and does not defer. If HAFDUP[BP No BackOff] is cleared, the eTSEC adheres to the truncated BEB
algorithm that allows the possibility of packets being received. This also can be detrimental in that packets
can now experience excessive collisions, causing them to be dropped in the stations from which they
originate. To reduce the likelihood of lost packets and packets leaking through the back pressure
mechanism, HAFDUP[BP No BackOff] must be set.
The eTSEC drops carrier (cease transmitting preamble) periodically to avoid excessive defer conditions in
other stations on the shared network. If, while applying back pressure, the eTSEC is requested to send a
packet, it stops sending preamble, and waits one IPG before sending the packet. HAFDUP[BP No
BackOff] applies for any collision that occurs during the sending of this packet. Collisions for packets
while half duplex back pressure is asserted are counted. The eTSEC does not defer while attempting to
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor
15-65