MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 729

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Synchronous Burst Read
Figure 14-90
HRDE, and HBRST on the first HCLKIN rising edge on which HCS is asserted. If HCID[0:3] match the
CHIPID value, the DSI is accessed.
HRDE and HBRST are asserted and HWBE are negated. When the DCR[8]:RPE bit (see the MSC8102
documentation) is set, a burst read access initiates data prefetching from consecutive addresses in the
internal memory space. Assertion of HTA indicates that data is valid for the current beat of the access and
the host must proceed to the next beat of this access. Because HTA is connected to the LUPWAIT signal
of the UPM, all local bus signals are frozen until HTA goes to 0 and then the UPM continues in its pattern.
When the host reaches the last beat of the access, it must terminate the burst access. The HTA is asserted
earlier when the data for this access is already prefetched to the read buffer. Typically, after the first beat
of the burst access, HTA remains asserted until the end of the access. After the last beat of the access, HTA
is driven to 1 and stops being driven in the next rising edge of HCLKIN. The host can start its next access
to the same MSC8102 immediately in the next
accesses. If the next access is not to the same MSC8102, to prevent contention on HTA, the host must wait
to access the next device until the previous DSI stops driving the HTA signal. The easiest way to achieve
this is insert idle cycles at the end of the UPM pattern to guarantee that HTA is inactive.
14.5.6.2.3
Using HBCS, a host can share one chip-select signal between multiple MSC8102 devices for broadcasting
write accesses. In broadcast mode, the DSI does not drive its HTA signal to prevent contention between
multiple devices driving different values to the same signal. Also, the DSI does not decode HCID[0:3].
Freescale Semiconductor
HWBE[0:7]
Legend:
HDST[0:1]
Timing conventions:
HA[11:29]
HCID[0:3]
1
0
1
0
HD[0:63]
HCLKIN
HBRST
HRDE
HCS
shows a synchronous burst read access. The DSI samples HA, HDST, HCID, HWBE,
HTA
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Broadcast Accesses
Valid value that can be 1 or 0
Don’t care
Three-state output signal that is not driven by the DSI
Figure 14-90. Synchronous Burst Read from MSC8102 DSI
A
D(A)
D(A+1)
H
CLKIN rising edge without negating HCS between
D(A+2)
n = 3 in 64-bit data bus interface
n = 7 in 32-bit data bus interface
D(A+2)
D(A+ n )
Local Bus Controller
14-111