MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 218

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Register Summary
6-2
1
2
3
4
5
pmr 128–131 UPMLCa0–3
pmr 256–259 UPMLCb0–3
0
USPRG0 is a separate physical register from SPRG0.
The 64-bit GPR registers are accessed by the SPE as separate 32-bit registers by SPE instructions. Only SPE vector instructions can access the upper word.
These registers are defined by the EIS and are not part of the Book E architecture.
e500v2 only
These registers are e500-specific
(upper) GPR0
pmr 384 UPMGC0
pmr 0–3
spr 570 MCSRR0
spr 571 MCSRR1
spr 572
spr 573
spr 569
spr 308
spr 309
spr 310
spr 304
spr 312
spr 313
spr 316
spr 317
Performance Monitor Registers
spr 63
spr 26
spr 27
spr 58
spr 59
spr 62
spr 61
General-Purpose Registers
GPR31
31 32
GPR1
GPR2
32
(read-only PMRs)
UPMCs
MCARU
Debug Registers
2
CSRR0
CSRR1
MCSR
DBCR0
DBCR1
DBCR2
MCAR
SRR0
SRR1
DEAR
DBSR
DAC1
DAC2
IVPR
IAC1
IAC2
ESR
(lower)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
3
63
3
63
4
3
3
3
3
3
General-
purpose
registers
Global control register
Counter
registers 0–3
Local control registers
a0–a3
Local control registers
b0–b3
Interrupt vector
prefix
Save/restore
registers 0/1
Critical SRR 0/1
Machine check
SRR 0/1
Exception syndrome
register
Machine check
syndrome register
Machine check
address register
Machine check
address register upper
Data exception
address register
Debug control
registers 0–2
Debug status register
Instruction address
compare
registers 1–4
Data address
compare
registers 1 and 2
Interrupt Registers
0
Figure 6-1. Core Register Model
spr 1012 MMUCSR0
spr 1015 MMUCFG
spr 1010
spr 1011
MMU Control and Status (read/write)
MMU Control and Status (read only)
spr 512 SPEFSCR
spr 513
spr 514
spr 400
spr 401
spr 415
spr 528
spr 529
spr 530
spr 531
spr 624
spr 625
spr 626
spr 627
spr 628
spr 630
spr 944
spr 633
spr 634
spr 688 TLB0CFG
spr 689 TLB1CFG
Instruction-Accessible Registers
spr 48
Supervisor-Level Registers
spr 9
spr 8
spr 1
31 32
ACC
Miscellaneous Registers
User-Level Registers
L1 Cache (read/write)
32
3
L1CSR0
L1CSR1
BBEAR
IVOR32
IVOR33
IVOR34
IVOR35
BBTAR
IVOR15
MAS0
MAS1
MAS2
MAS3
MAS4
MAS6
MAS7
IVOR0
IVOR1
PID1
PID2
PID0
CTR
• • •
XER
CR
LR
3
3
3
3
3
3
3
3
4
3
3
3
3
3
3
63
63
3
3
3
3
3
3
3
Condition register
Count register
Link register
Integer exception
register
SPE FP status/control
register
Accumulator
Branch buffer entry
address register
Branch buffer target
address register
Interrupt vector offset
registers 0–15
Interrupt vector offset
registers 32–35
MMU control and status
register 0
MMU assist
registers
0–4 and 6
Process ID
registers 0–2
MMU configuration
TLB configuration 0/1
L1 Cache
Control/Status 0/1
pmr 144–147 PMLCa0–3
pmr 272–275 PMLCb0–3
spr 272–279
pmr 16–19
spr 1023
spr 1008
spr 1009
spr 1013
pmr 400
spr 256
spr 259
spr 260
spr 263
spr 268
spr 269
spr 515
spr 516
spr 286
spr 287
spr 284
spr 285
spr 340
spr 336
Performance Monitor Registers
Time-Base Registers (read only)
spr 22
spr 54
User General SPR (read/write)
Timer/Decrementer Registers
Miscellaneous Registers
General SPRs (read only)
Configuration Registers
L1 Cache (read only)
32
32
SPRG0–7
L1CFG0
L1CFG1
PMC0–3
USPRG0
BUCSR
PMGC0
SPRG3
SPRG4
SPRG7
DECAR
HID0
HID1
MSR
• • •
SVR
PVR
DEC
TCR
TSR
TBU
TBU
TBL
PIR
TBL
Freescale Semiconductor
3
3
5
3
63
3
3
63
3
3
3
Timer control
User SPR
general 0
SPR general
registers 3–7
Time base
lower/upper
L1 cache
configuration registers
0–1
Machine state
System version
Processor ID
Processor version
Decrementer
Decrementer
auto-reload
Time base
lower/upper
Timer status
Hardware
implementation
dependent 0–1
Branch control and
status register
General SPRs 0–7
Global control
Counter registers 0–3
Local control a0–a3
Local control b0–b3
1