MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 756

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15-26
Bits
10
11
12
13
14
15
16
6
7
8
9
Name
GTSC
XFUN
BABT
RXB
TXC
TXE
TXB
CRL
TXF
LC
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
the transmitter is put into a pause state after completion of the frame currently being transmitted.
0 No graceful stop interrupt.
1 Graceful stop requested.
MAC’s maximum frame length register and MACCFG2[Huge Frame] is cleared. Frame truncation occurs
when this condition occurs.
0 Transmitted frame length not exceeding maximum frame length.
1 Transmitted frame length exceeding maximum frame length when MACCFG2[Huge Frame] = 0.
0 Control frame not transmitted.
1 Control frame transmitted.
TSTAT[THLT] to be set by the eTSEC. This bit is set whenever any transmit error occurs that causes the
transmitter to halt (EBERR, LC, CRL, XFUN).
0 No transmit channel error occurred.
1 Transmit channel error occurred.
set in its status word and was not the last buffer descriptor of the frame.
0 No transmit buffer descriptor updated.
1 Transmit buffer descriptor updated.
transmit buffer descriptor (TxBD) was updated. This only occurs if the I (interrupt) bit in the status word of
the buffer descriptor is set. The specific transmit queue that was updated has its TXF bit set in TSTAT.
0 No frame transmitted/TxBD not updated.
1 Frame transmitted/TxBD updated.
Reserved
Late collision. This bit indicates that a collision occurred beyond the collision window (slot time) in
half-duplex mode. The frame is truncated with a bad CRC and the remainder of the frame is discarded.
0 No late collision occurred.
1 Late collision occurred.
the MAC’s half-duplex register’s retransmission maximum count (HAFDUP[Retransmission Maximum]). The
frame is discarded without being transmitted and transmission of the next frame commences. This only
occurs while in half-duplex mode.
0 Successive transmission collisions do not exceed maximum.
1 Successive transmission collisions exceed maximum.
was transmitted.
0 Transmit FIFO not underrun.
1 Transmit FIFO underrun.
set in its status word and was not the last buffer descriptor of the frame.
0 Receive buffer descriptor not updated.
1 Receiver buffer descriptor updated.
Graceful transmit stop complete. This interrupt is asserted for one of two reasons. Graceful stop means that
Babbling transmit error. This bit indicates that the transmitted frame length has exceeded the value in the
Transmit control interrupt. This bit indicates that a control frame was transmitted.
Transmit error. This bit indicates that an error occurred on the transmitted channel that has caused
Transmit buffer. This bit indicates that a transmit buffer descriptor was updated whose I (interrupt) bit was
Transmit frame interrupt. This bit indicates that a frame was transmitted and that the last corresponding
Collision retry limit. This bit indicates that the number of successive transmission collisions has exceeded
Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before the complete frame
Receive buffer. This bit indicates that a receive buffer descriptor was updated which had the I (Interrupt) bit
• A graceful stop, which was initiated by setting DMACTRL[GTS], is now complete.
• A transmission of a flow control PAUSE frame, which was initiated by setting TCTRL[TFC_PAUSE], is
now complete.
Table 15-7. IEVENT Field Descriptions (continued)
Description
Freescale Semiconductor