MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 205

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Each interrupt has an associated interrupt vector address, obtained by concatenating the IVPR value with
the address index in the associated IVOR (that is, IVPR[32–47] || IVORn[48–59] || 0b0000). The resulting
address is that of the instruction to be executed when that interrupt occurs. IVPR and IVOR values are
indeterminate on reset, and must be initialized by the system software using mtspr.
registers implemented on the e500 and the associated interrupts.
Freescale Semiconductor
SPEFSCR Signal processing and embedded floating-point status and control register—Provides interrupt control and status
Register
MCAR
MCSR
IVORs
DEAR
IVPR
ESR
Machine check address register—Holds the address of the data or instruction that caused the machine check
interrupt. MCAR contents are not meaningful if a signal triggered the machine check interrupt.
Machine check syndrome register—Holds machine state information on machine check interrupts and restores
machine state after an rfmci instruction is executed.
Exception syndrome register—Provides a syndrome to differentiate between the different kinds of exceptions that
generate the same interrupt type. Upon generation of a specific exception type, the associated bit is set and all
other bits are cleared.
as well as various condition bits associated with the operations performed by the SPE.
Data exception address register—Holds the address that was referenced by a load, store, or cache management
instruction that caused an alignment, data TLB miss, or data storage interrupt.
Together, IVPR[32–47] || IVOR n [48–59] || 0b0000 define the address of an interrupt-processing routine. See
Table 5-7
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Register
IVOR10
IVOR11
IVOR12
IVOR13
IVOR0
IVOR1
IVOR2
IVOR3
IVOR4
IVOR5
IVOR6
IVOR7
IVOR8
IVOR9
and the EREF for more information.
Table 5-7. Interrupt Vector Registers and Exception Conditions
Critical input
Machine check interrupt offset
Data storage interrupt offset
Instruction storage interrupt offset
External input interrupt offset
Alignment interrupt offset
Program interrupt offset
Floating-point unavailable interrupt offset
System call interrupt offset
Auxiliary processor unavailable interrupt offset
Decrementer interrupt offset
Fixed-interval timer interrupt offset
Watchdog timer interrupt offset
Data TLB error interrupt offset
Table 5-6. Interrupt Registers (continued)
Embedded Category–Defined IVORs
Other Interrupt Registers
SPE Interrupt Registers
Syndrome Registers
Description
Interrupt
Table 5-7
Core Complex Overview
lists IVOR
5-21