MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 155

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

3.2
The signals that serve alternate functions as configuration input signals during system reset are
summarized in
Chapter 4, “Reset, Clocking, and Initialization.”
Note that throughout this document, the reset configuration signals are described as being sampled at the
negation of HRESET. However, there is a setup and hold time for these signals relative to the rising edge
of HRESET, as described in the MPC8533E Integrated Processor Hardware Specifications. Note that the
PLL configuration signals have different setup and hold time requirements than the other reset
configuration signals.
The reset configuration signals are multiplexed with other functional signals. The values on these signals
during reset are interpreted to be logic one or zero, regardless of whether the functional signal name is
defined as active-low. Most of the reset configuration signals have internal pull-up resistors so that if the
signals are not driven, the default value is high (a one), as shown in the table. Some signals do not have
pull-up resistors and must be driven high or low during the reset period. For details about all the signals
that require external pull-up resistors, see the MPC8533E Integrated Processor Hardware Specifications.
Freescale Semiconductor
UART_SOUT[0:1]
TSEC3_RXD[7:0]
TSEC3_TXD[1:0]
TSEC3_TXD[6:4]
TSEC3_TX_CLK
TSEC3_RX_DV
TSEC3_RX_ER
UART_CTS[0:1]
UART_RTS[0:1]
TSEC3_TX_EN
TSEC3_TX_ER
UART_SIN[0:1]
TSEC3_TXD2
TSEC3_TXD3
TSEC3_TXD7
Name
UDE
Configuration Signals Sampled at Reset
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table
TSEC3 receive data valid
TSEC3 receive error
TSEC3 receive data 7–0
TSEC3 transmit clock in
TSEC3 transmit enable
TSEC3 transmit error
TSEC3 transmit data 1–0
TSEC3 transmit data [6:4]
TSEC3 transmit data 2
TSEC3 transmit data 3
TSEC3 transmit data 7
DUART clear to send
DUART ready to send
DUART serial data in
DUART serial data out
Unconditional debug event
3-3. The detailed interpretation of their voltage levels during reset is described in
Description
Table 3-2. Alphabetical Signal Reference (continued)
Functional
Dual UART
Dual UART
Dual UART
Dual UART
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
Block
PIC
Alternate Function(s)
cfg_etsec3_prtcl[1:0]
cfg_etsec3_reduce
/cfg_io_ports[0:2]
cfg_etsec3_serial
FIFO3_RXD[7:0]
FIFO3_TXD[1:0]
FIFO3_TXD[6:4]
FIFO3_TX_CLK
FIFO3_RX_DV
FIFO3_RX_ER
FIFO3_TX_EN
FIFO3_TX_ER
FIFO3_TXD2
FIFO3_TXD3
FIFO3_TXD7
—
—
—
—
—
Signals
No. of
1
1
8
1
1
1
2
3
1
1
1
2
2
2
2
1
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Signal Descriptions
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
15-2/15-9
13-2/13-3
13-2/13-3
10-5/10-8
13-2/13-3
13-2/13-3
Table/
Page
3-15