MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 533

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.4.5
This register, shown in
self-clearing bits.
Table 12-30
12.4.4.6
This status register, as seen in
of these internal signals reflect the state of low-level MDEU functions, such as data padding, key padding,
etc., and are not important to the user; however the user should be aware that reads of this register,
Freescale Semiconductor
Offset MDEU 0x3_6010
Reset
0–60
Offset MDEU 0x3_6018
Reset
Bits Name
61
62
63
W
W
R
R
0
0
SR
MI
—
RI
describes MDEU reset control register fields.
Reserved
Reset interrupt. Writing this bit active high causes MDEU interrupts signaling DONE and ERROR to be reset. It
further resets the state of the MDEU interrupt status register.
0 No reset
1 Reset interrupt logic
Module initialization is nearly the same as software reset, except that the MDEU interrupt control register remains
unchanged.
0 No reset
1 Reset most of MDEU
Software reset is functionally equivalent to hardware reset (the RESET signal), but only for the MDEU. All
registers and internal state are returned to their defined reset state.
0 No reset
1 Full MDEU reset
MDEU Reset Control Register (MDEURCR)
MDEU Status Register (MDEUSR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Writing to the data size register will allow the MDEU to enter auto-start
mode. Therefore, the required context registers must be written prior to
writing the data size.
Table 12-30. MDEU Reset Control Register Field Descriptions
Figure
Figure
12-33, allows three levels of reset for the MDEU, as defined by the three
Figure 12-33. MDEU Reset Control Register
Figure 12-32. MDEU Data Size Register
12-34, reflects the state of the MDEU internal signals. The majority
—
NOTE
—
All zeros
All zeros
Description
47 48
Security Engine (SEC) 2.1
DATA SIZE
Access: Read/Write
Access: Read/Write
RI MI SR
61 62
12-55
63
63