MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1063

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The fields of the PCI Express PME and message disable register are described in
Freescale Semiconductor
23–24
0–15
Bits
16
17
18
19
20
21
22
25
26
27
28
29
30
31
ENL23D Entered_L2/L3 ready disable. When set will disable the setting of PEX_PME_MES_DR[ENL23] bit.
EXL23D Exited_L2/L3 ready disable. When set will disable the setting of PEX_PME_MES_DR[EXL23] bit.
AIOND
PIOND
PTATD
AIOFD
PIOFD
HRDD
Name
PTOD
LDDD
ABPD
AIBD
PIBD
—
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
PME turn off disable. When set will disable the setting of PEX_PME_MES_DR[PTO] bit.
1 Disable PME_Turn_Off_message detection
0 Enable PME_Turn_Off message detection
PME to ack time-out disable. When set will disable the setting of PEX_PME_MES_DR[PTAT] bit.
1 Disable PME_TO_Ack time-out detection
0 Enable PME_TO_Ack time-out detection
1 Disable Entered_L2/L3 ready state detection
0 Enable Entered_L2/L3 ready state detection
1 Disable Exited_L2/L3 ready state detection
0 Enable Exited_L2/L3 ready state detection
Reserved
Hot reset detected disable. When set will disable the setting of PEX_PME_MES_DR[HRD] bit.
1 Disable hot reset state detection
0 Enable hot reset state detection
Link down detected disable. When set will disable the setting of PEX_PME_MES_DR[LDD] bit.
1 Disable link down state detection
0 Enable link down state detection
Reserved
Attention indicator on disable. When set will disable the setting of PEX_PME_MES_DR[AION] bit.
1 Disable attention indicator on message detection
0 Enable attention indicator on message detection
Attention indicator blink disable. When set will disable the setting of PEX_PME_MES_DR[AIB] bit.
1 Disable attention indicator blink message detection
0 Enable attention indicator blink message detection
Attention indicator off disable. When set will disable the setting of PEX_PME_MES_DR[AIOF] bit.
1 Disable attention indicator off message detection
0 Enable attention indicator off message detection
Power indicator on disable. When set will disable the setting of PEX_PME_MES_DR[PION] bit.
1 Disable power indicator on message detection
0 Enable power indicator on message detection
Power indicator blink disable. When set will disable the setting of PEX_PME_MES_DR[PIB] bit.
1 Disable power indicator blink message detection
0 Enable power indicator blink message detection
Power indicator off disable. When set will disable the setting of PEX_PME_MES_DR[PIOF] bit.
1 Disable power indicator off message detection
0 Enable power indicator off message detection
Attention button pressed disable. When set will disable the setting of PEX_PME_MES_DR[ABP] bit.
1 Disable attention button press message detection
0 Enable attention button press message detection
Table 18-10. PEX_PME_MES_DISR Field Descriptions
Description
PCI Express Interface Controller
Table
18-10.
18-15