MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 149

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
SD1_REF_CLK,
SD2_REF_CLK,
SD1_REF_CLK
SD2_REF_CLK
HRESET_REQ
SD1_RX[7:4],
LSSD_MODE
SD1_TX[3:0],
SD1_TX[7:4],
CKSTP_OUT
SD1_RX[7:4]
MSRCID[2:4]
SD1_TX[3:0]
SD1_TX[7:4]
GPOUT[0:7]
L1_TSTCLK
L2_TSTCLK
SD2_RX[0],
SD2_TX[0],
SD2_RX[0]
TRIG_OUT
TEST_SEL
SD2_TX[0]
CKSTP_IN
GPIN[0:7]
MSRCID0
MSRCID1
HRESET
SRESET
ASLEEP
TRIG_IN
READY
MDVAL
Name
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 3-1.
Receive data,
receive data complement
Transmit data,
transmit data complement
Transmit data,
transmit data complement
SerDes1 reference clock,
SerDes1 reference clock
complement
Receive data,
receive data complement
Transmit data,
transmit data complement
SerDes2 reference clock,
SerDes2 reference clock
complement
Hard reset
Hard reset request
Soft reset
Checkstop in
Checkstop out
General-purpose output
General-purpose input
Device ready
Asleep
Watchpoint trigger in
Watchpoint trigger out
Memory debug source port
ID 0
Memory debug source port
ID 1
Memory debug source port
ID 2–4
Memory debug data valid
LSSD mode
L1 test clock
L2 test clock
Test select
Description
MPC8533E
Signal Reference by Functional Block (continued)
purpose outputs
PCI Express 1,
System control
System control
System control
System control
System control
purpose inputs
System control
PCI Express 2
PCI Express 1
PCI Express 2
PCI Express 2
PCI Express 3
PCI Express 3
PCI Express 3
Power mgmt
Functional
General-
General-
Debug
Debug
Debug
Debug
Debug
Debug
Block
Test
Test
Test
Test
Alternate Function(s)
cfg_mem_debug
cfg_ddr_debug
TRIG_OUT
READY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Signals
No. of
2
8
1
1
8
8
8
4
4
2
1
1
1
1
1
8
1
1
1
1
3
1
1
1
1
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Signal Descriptions
19.4.1.9/19-12
19.4.1.9/19-12
18-2/18-5
18-2/18-5
18-2/18-5
18-2/18-5
18-2/18-5
18-2/18-5
18-2/18-5
19-2/19-2
19-2/19-2
19-2/19-2
19-2/19-2
19-2/19-2
21-4/21-7
21-4/21-7
21-3/21-6
21-3/21-6
21-3/21-6
21-3/21-6
21-5/21-8
21-5/21-8
21-5/21-8
21-5/21-8
4-2/4-2
4-2/4-2
4-2/4-2
4-2/4-2
Table/
Page
3-9