MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 69

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table
Number
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
7-23
7-24
7-25
Freescale Semiconductor
MAS3 Field Descriptions–RPN and Access Control ........................................................... 6-37
MAS4 Field Descriptions—Hardware Replacement Assist Configuration.......................... 6-38
MAS6—TLB Search Context Register 0.............................................................................. 6-39
MAS 7 Field Descriptions—High Order RPN ..................................................................... 6-39
DBCR0 Field Descriptions ................................................................................................... 6-40
DBCR1 Field Descriptions ................................................................................................... 6-41
DBCR2 Field Descriptions ................................................................................................... 6-42
DBSR Field Descriptions...................................................................................................... 6-44
SPEFSCR Field Descriptions................................................................................................ 6-45
ACC FIeld Descriptions........................................................................................................ 6-47
Supervisor-Level PMRs (PMR[5] = 1) ................................................................................. 6-48
User-Level PMRs (PMR[5] = 0) (Read Only)...................................................................... 6-48
PMGC0 Field Descriptions ................................................................................................... 6-49
PMLCa0–PMLCa3 Field Descriptions ................................................................................. 6-50
PMLCb0–PMLCb3 Field Descriptions ................................................................................ 6-51
PMC0–PMC3 Field Descriptions ......................................................................................... 6-52
Available L2 Cache/SRAM Configurations............................................................................ 7-3
Way Selection for SRAM Accesses........................................................................................ 7-6
L2/SRAM Memory-Mapped Registers................................................................................... 7-9
L2CTL Field Descriptions .................................................................................................... 7-10
L2CEWARn Field Descriptions............................................................................................ 7-14
L2CEWAREAn Field Descriptions ...................................................................................... 7-14
L2CEWCRn Field Descriptions............................................................................................ 7-15
L2SRBARn Field Descriptions............................................................................................. 7-16
L2SRBAREAn Field Descriptions ....................................................................................... 7-17
L2ERRINJHI Field Description............................................................................................ 7-18
L2ERRINJLO Field Description .......................................................................................... 7-19
L2ERRINJCTL Field Descriptions....................................................................................... 7-19
L2CAPTDATAHI Field Description..................................................................................... 7-20
L2CAPTDATALO Field Description.................................................................................... 7-20
L2CAPTECC Field Descriptions .......................................................................................... 7-21
L2ERRDET Field Descriptions ............................................................................................ 7-21
L2ERRDIS Field Descriptions.............................................................................................. 7-22
L2ERRINTEN Field Descriptions ........................................................................................ 7-23
L2ERRATTR Field Descriptions .......................................................................................... 7-23
L2ERRADDRH Field Description ....................................................................................... 7-24
L2ERRADDRL Field Description........................................................................................ 7-25
L2ERRCTL Field Descriptions ............................................................................................ 7-25
Fastest Read Timing—Hit in L2 ........................................................................................... 7-27
PLRU Bit Update Algorithm ................................................................................................ 7-32
PLRU-Based Victim Selection Mechanism .......................................................................... 7-33
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Tables
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Number
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