MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 187

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The Power Architecture technology defines categories that extend the architecture that can perform
computational or system management functions. One of these on the e500 is the signal processing engine
(SPE), which includes a suite of vector instructions that use the upper and lower halves of the GPRs as a
single two-element operand. Some extensions are defined by Freescale’s embedded category
implementation standards (EIS).
5.1.1
The e500 provides 32-bit effective addresses and integer data types of 8, 16, and 32 bits, as defined by the
architecture. It also provides two-element, 64-bit data types for the SPE and embedded vector
floating-point instructions, which include instructions that operate on operands comprised of two 32-bit
elements. It also provides a 64-bit scalar data type for use with embedded double-precision floating-point
instructions.
The embedded single-precision scalar floating-point instructions use 32-bit single-precision instructions.
5.1.2
The core complex is a superscalar processor that can issue two instructions and complete two instructions
per clock cycle. Instructions complete in order, but can execute out of order. Execution results are available
to subsequent instructions through the rename buffers, but those results are recorded into architected
registers in program order, maintaining a precise exception model. All arithmetic instructions that execute
in the core operate on data in the GPRs. Although the GPRs are 64 bits wide, only SPE, DPFP (e500v2
only), and embedded vector floating-point instructions operate on the upper word of the GPRs; the upper
32 bits are not affected by other 32-bit instructions.
The processor core integrates two simple instruction units (SU1, SU2), a multiple-cycle instruction unit
(MU), a branch unit (BU), and a load/store unit (LSU).
The LSU and SU2 support 64- and 32-bit instructions.
The ability to execute five instructions in parallel and the use of simple instructions with short execution
times yield high efficiency and throughput. Most integer instructions execute in 1 clock cycle. A series of
Freescale Semiconductor
Upward Compatibility
Core Complex Summary
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
The SPE (which includes embedded floating-point functionality) is
implemented in all PowerQUICC III devices. However, these instructions
will not be supported in devices subsequent to PowerQUICC III. Freescale
Semiconductor strongly recommends that use of these instructions be
confined to libraries and device drivers. Customer software that uses SPE or
embedded floating-point instructions at the assembly level or that uses SPE
intrinsics will require rewriting for upward compatibility with
next-generation PowerQUICC devices.
Freescale Semiconductor offers a libcfsl_e500 library that uses SPE
instructions. Freescale will also provide libraries to support next-generation
PowerQUICC devices.
NOTE
Core Complex Overview
5-3