MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 508

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
Table 12-12
12.4.1.7
The interrupt status register tracks the state of possible errors—if those errors are not masked—via the
PKEU interrupt control register. The definition of each bit in the PKEU interrupt status register is shown
in
12-30
Offset PKEU 0x3_C030
Reset
59–60
0–56
Bits
57
58
61
62
63
Figure
W
R
0
Name
HALT Halt indicates that the PKEU has halted due to an error.
RD
—
—
IE
ID
Z
12-13.
describes the PKEU status register fields.
PKEU Interrupt Status Register (PKEUISR)
Reserved
Zero. This bit reflects the state of the PKEU zero detect bit when last sampled. Only particular instructions within
routines cause zero to be modified, so this bit should be used with great care.
0 PKEU not halted
1 PKEU halted
Note: Because the error causing the PKEU to stop operating may be masked before reaching the interrupt
Reserved
Interrupt error. This status bit reflects the state of the ERROR interrupt signal, as sampled by the controller
interrupt status register
0 PKEU is not signaling error
1 PKEU is signaling error
Interrupt done. This status bit reflects the state of the DONE interrupt signal, as sampled by the controller
interrupt status register
0 PKEU is not signaling done
1 PKEU is signaling done
Reset done. This status bit, when high, indicates that PKEU has completed its reset sequence, as reflected in
the signal sampled by the appropriate channel.
0 Reset in progress
1 Reset done
Note: Reset done resets to 0, but has typically switched to 1 by the time a user checks the register, indicating
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
status register, the PKEU interrupt status register is used to provide a second source of information
regarding errors preventing normal operation.
the EU is ready for operation.
Table 12-12. PKEU Status Register Field Descriptions
Figure 12-13. PKEU Interrupt Status Register
(Section 12.6.5.3, “Interrupt Status Register
(Section 12.6.5.3, “Interrupt Status Register
—
All zeros
Description
49
INV IE — CE KSE DSE ME AE
50
51 52 53
(ISR)”).
(ISR)”).
54
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55
56
57 58
Access: Read
—
63