MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 179

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Note that the value latched on this signal during POR is accessible through the memory-mapped
PORDBGMSR (POR debug mode register) described in
Register (PORDBGMSR).”
4.4.3.20
The LBC address/data bus inputs, shown in
configuration register defined in
(GPPORCR).”
LAD[0:31] during POR is captured and stored (read only) in the GPPORCR. Software can then use this
value to inform the operating system about initial system configuration. Typical interpretations include
circuit board type, board ID number, or a list of available peripherals.
4.4.4
The following paragraphs describe the clocking within the MPC8533E device.
4.4.4.1
The MPC8533E takes a single input clock, SYSCLK, as its primary clock source for the e500 core and all
of the devices and interfaces that operate synchronously with the core. As shown in
SYSCLK input (frequency) is multiplied up using a phase lock loop (PLL) to create the core complex bus
(CCB) clock (also called the platform clock). The CCB clock is used by virtually all of the synchronous
system logic, including the L2 cache, and other internal blocks such as the DMA and interrupt controller.
The CCB clock also feeds the PLL in the e500 core and the PLL that create clocks for the local bus memory
controller. Note that the divide-by-two CCB clock divider and the divide-by-n CCB clock divider, shown
in
The PCI interface may use SYSCLK as the PCI clock and thus have PCI operation be synchronous with the
platform. Alternately, a separate, independent clock may be used for the PCI interface, in which case PCI
operation is asynchronous with respect to SYSCLK and the platform clock.
Freescale Semiconductor
Functional
Default (1)
MSRCID1
Functional
Signal
Figure
No default
LAD[0:31]
Signals
4-6, are located in the DDR and local bus blocks, respectively.
Reset Configuration
Clocking
General-Purpose POR Configuration
System Clock/PCI Clock
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
cfg_ddr_debug
Reset Configuration
This register is intended to facilitate POR configuration of user systems. A value placed on
cfg_gpinput[0:31]
Name
Name
Table 4-28. General-Purpose POR Configuration
(Binary)
Value
Section 19.4.1.7, “General-Purpose POR Configuration Register
0
1
Table 4-27. DDR Debug Configuration
(Binary)
Value
—
Debug information is driven on the ECC pins instead of normal ECC I/O. ECC
signals from memory devices must be disconnected.
Debug information is not driven on ECC pins. ECC pins function in their normal
mode (default).
General-purpose POR configuration vector to be placed in GPPORCR
Table
4-28, configure the value of the general-purpose POR
Section 19.4.1.5, “POR Debug Mode Status
Meaning
Meaning
Reset, Clocking, and Initialization
Figure
4-6, the
4-21