MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 857

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

15.6.1.1
This section describes the media-independent interface (MII) intended to be used between the PHYs and
the eTSEC.
establish eTSEC module connection with a PHY.
An MII interface has 18 signals (including the TSECn_MDC and TSECn_MDIO signals), as defined by
the IEEE 802.3u standard, for connecting to an Ethernet PHY.
15.6.1.2
This section describes the reduced media-independent interface (RMII) intended to be used between the
PHYs and the GMII MAC. The RMII is a reduced-pin alternative to the IEEE802.3u MII. The RMII
reduces the number of signals required to interconnect the MAC and the PHY from a maximum of 18
signals (MII) to 10 signals. To accomplish this objective, the data paths are halved in width and clocked at
twice the MII clock frequency, while clocks, carrier sense and error signals have been partly combined.
For 100 Mbps operation, the reference clock operates at 50 MHz, whereas for 10 Mbps operation, the
clock remains at 50MHz, but only every 10th cycle is used.
of the reduced media-independent interface and the signals required to establish an eTSEC’s connection
with a PHY. The RMII is implemented as defined by the RMII Specification of the RMII Consortium, as
of March 20, 1998.
Freescale Semiconductor
1
The management signals (MDC and MDIO) are common to all of the Ethernet controllers’ connections
in the system, assuming that each PHY has a different management address.
eTSEC
Figure 15-117
Media-Independent Interface (MII)
Reduced Media-Independent Interface (RMII)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
depicts the basic components of the MII including the signals required to
Receive Data Valid (TSECn_RX_DV)
Carrier Sense Output (TSECn_CRS)
Transmit Enable (TSECn_TX_EN)
Transmit Clock (TSECn_TX_CLK)
Receive Clock (TSECn_RX_CLK)
Transmit Data (TSECn_TXD[3:0])
Receive Data (TSECn_RXD[3:0])
Management Data Clock1 (MDC)
Figure 15-117. eTSEC-MII Connection
Transmit Error (TSECn_TX_ER)
Receive Error (TSECn_RX_ER)
Management Data I/O1 (MDIO)
Collision Detect (TSECn_COL)
Figure 15-118
Enhanced Three-Speed Ethernet Controllers
depicts the basic components
Ethernet
10/100
PHY
Medium
15-127